1. Field of the Invention
The present invention relates to a multiplex time division switching network and, more particularly, to a switching network of the type concerned having two time division stages, commonly called "TT" type.
2. Description of the Prior Art
The structure of an elementary multiplex time division switching network will first be reminded.
As it is well known, a multiplex time division switching network is an operator device which allows to transmit in whatever given order in the time slots of an outgoing multiplex highway information samples or words which are received in sequential order in the time slots of an incoming multiplex highway. This kind of operator device comprises a buffer store in which the words written in the time slots of the incoming multiplex highway are written in sequentially during a frame interval and a control store which controls the reading out of these words at times which correspond to the time slots of the outgoing multiplex highway which they are assigned to.
It is also well known that the multiplex time division switching networks can be input controlled or output controlled. In the multiplex time division switching networks which are output controlled, the word locations in the buffer store are assigned to the time slots of the incoming multiplex highway. In other words, the words are stored in the buffer store according to their serial order in the incoming multiplex highway. At each instant corresponding to a time slot of the outgoing multiplex highway, the control store sends to the buffer store an order to read out the word to be inserted into this outgoing multiplex highway time slot together with the address at which this word is to be read out in the buffer store. In the input controlled multiplex time division switching networks, the word locations in the buffer store are assigned to the time slots of the outgoing multiplex highway. At each instant corresponding to a time slot of the incoming multiplex highway, the control store sends to the buffer store an order to write in the word to be extracted from this incoming multiplex highway time slot together with the address at which this word is to be written in the buffer store.
Briefly, it can be said that, in the output controlled multiplex time division switching networks, writing in is cyclic while reading out is controlled by the control store and that, in the input controlled multiplex time division switching networks, reading out is cyclic while writing in is controlled by the control store.
Let us assume that time slot t.sub.1 (0.ltoreq.i.ltoreq.k-1) of the incoming multiplex highway is to be switched to time slot t.sub.j (0.ltoreq.j.ltoreq.k-1) of the outgoing multiplex highway in a multiplex time division switching network controlled by its output. The buffer store has k word locations having each b bits, i.e. as many word locations as the highways have time slots. The control store has k word locations having each log.sub.2 k bits. The buffer store has two addressing circuits, one for writing in the other for reading out. Each time slot t.sub.i is divided into two elementary time intervals t.sub.i,w and t.sub.i,r. During t.sub.i,w, the word located in time slot t.sub.i of the incoming multiplex highway is extracted from this time slot and written in the buffer store at address i. During t.sub.i,r, the word located at address i in the buffer store is read out from the buffer store and transferred into time slot t.sub.i of the outgoing multiplex highway.
Therefore, the connection t.sub.i .fwdarw.t.sub.j is implemented in two steps. At time t.sub.i,w, the word located in time slot t.sub.i of the incoming multiplex highway is written at address i in the buffer store and at time t.sub.j,r, the word located at address j in the control store is read out and sent to the buffer store. This word is the very address i at which the word to be written in time slot t.sub.j of the outgoing multiplex highway is stored in the buffer store.
The connection t.sub.i .fwdarw.t.sub.j in an input controlled multiplex time division switching network can be derived without difficulty from the previous explanations.
If there are N incoming multiplex highways and N outgoing multiplex highways each having k=32 time slots, the capacity of the buffer store and control store must be of 32.times.N words and the rate of writing in and reading out operations is EQU (2.times.32.times.10.sup.6)/125 N=512,000 N
if the frame duration is 125 .mu.s. If N=32, this rate becomes equal to 16.4.times.10.sup.6 operations per second.
It is possible to "supermultiplex" the N incoming multiplex highways and to "superdemultiplex" the N outgoing multiplex highways and provide a buffer store having a capacity of 32.times.N word locations. It is also possible neither to supermultiplex nor superdemultiplex the incoming and outgoing multiplex highways and provide N partial buffer stores having each 32 word locations, each partial buffer store being connected to a single incoming multiplex highway and to a single outgoing multiplex highway. Then N words can be simultaneously written into or read from the N partial buffer stores and the writing in and reading out operation rate becomes EQU (1+N) (32.times.10.sup.6)/125=256,000 (1+N)
If N=32, this rate becomes equal to 8.4.times.10.sup.6 operations per second.
An elementary multiplex time division switching network has the advantage of being without blocking, i.e. any time slot of any incoming multiplex highway can be switched to any time slot of any outgoing multiplex highway whatever may be the state of occupation of the other time slots. However, such a switching network has a limited capacity since the greater the number N of elementary highways the higher the operating rate of the buffer and control stores. Capacity is limited by technology. At the present time, one cannot exceed N=64 using fast memories implementing 16.times.10.sup.6 operations per second, i.e. with a cycle of 62 ns.
The structure of a two time stage multiplex time division switching network will now be reminded.
Such a switching network is composed by an input stage and an output stage each comprising P elementary multiplex time division switching networks. Each elementary multiplex time division switching network is connected to an incoming supermultiplex highway formed by the supermultiplexing of N incoming elementary multiplex highways and to an outgoing supermultiplex highway which is demultiplexed into N outgoing elementary multiplex highways. The input elementary multiplex time division switching networks are connected to the output elementary multiplex time division switching networks through multiplex links having (32 N/P) time slots per frame. There are P multiplex links outgoing from each input elementary multiplex time division switching network and each of said multiplex links is connected to an output elementary multiplex time division switching network.
The elementary switching networks of the input stage are input controlled and the elementary switching networks of the output stage are output controlled. A connection between elementary channel i (0.ltoreq.i.ltoreq.31) of incoming elementary multiplex highway IH.sub.n,p (0.ltoreq.n.ltoreq.N-1 and 0.ltoreq.p.ltoreq.P-1) and elementary channel j (0.ltoreq.j.ltoreq.31) of outgoing elementary multiplex highways OH.sub.m,q (0.ltoreq.m.ltoreq.N-1 and 0.ltoreq.q.ltoreq.P-1) is implemented as follows:
The information word in time slot i of incoming multiplex highway IH.sub.n,p is transferred during the supermultiplexing operation into time slot .alpha. of the incoming supermultiplex highway of serial number p and is written at address (.gamma.,q) in the buffer store of the input elementary switching network of serial number p which is input controlled. This buffer store address (.gamma.,q) is supplied by the input control store at address .alpha. of the latter. The information word is read out during time slot .gamma. of the multiplex link connecting the input elementary switching network of serial number p to the output elementary switching network of serial number q. This reading out is cyclic and performed by a time base. The output elementary switching network is output controlled. The information word in time slot .gamma. of the multiplex link is written at address (.gamma.,p) in the buffer store of this output elementary switching network under the control of the time base. The word in the buffer store is read out during time slot .beta. of the outgoing supermultiplex highway under the control of the output control store which contains (.beta.,p) at its address .beta.. Finally, the information word in time slot .beta. is transferred during the supermultiplexing operation into time slot j of outgoing multiplex highway OH.sub.m,q.
The number of unit memories (bit memories) of a "time-time" multiplex time division switching network dealing with P groups of N incoming and outgoing time slots is EQU 2(13+log.sub.2 N)
per elementary multiplex highway.